1. Field of the Invention
The present invention relates to a data processor with a cache system and data access method therefor, and more particularly, to a data processor with a cache system which provides simplified access control for a memory, high-speed processing of a CPU when the cache system misses, and a data access method.
2. Description of the Related Art
FIG. 1 is a block diagram of a peripheral portion of the CPU and cache of the invention disclosed in U.S. Pat. No. 5,185,879 which exemplifies a prior art data processor with a cache system.
This illustrated example shows a memory system 3 accessed merely by a block transfer mode which transfers multiple data from the memory system 3, when a cache 2 misses when the CPU 1 accesses to read a single data for the cache 2.
A system bus buffer 6 is the common interface between the CPU 1 and cache 2 and a system bus SB.
Signals being sent and received between the CPU 1, cache 2, and system bus buffer 6 can be roughly divided into control signals, address signals, and data signals.
A control signal SCa is used as a duplex common control signal between the CPU 1, cache 2, and system bus buffer 6. A control signal SCb which is used only where the CPU 1 is a bus master is used as both a duplex signal between the CPU 1 and cache 2 and as a duplex signal between the CPU 1 and multiplexer 7. Furthermore, a control signal CSCb which is used only where the cache 2 is the bus master is used as a duplex signal between the cache 2 and multiplexer 7.
When outputting data, in response to a multiplexer control signal SC1 outputted from the cache 2, the multiplexer 7 selects either the control signal SCb or CSCb to output as a control signal SCc to the system bus buffer 6. When inputting data, in response to the multiplexer control signal SC1, the multiplexer 7 has a function for sending the control signal SCc from the system bus buffer 6 as the control signal SCb to the CPU 1 or sending SCc to the CPU 1 as control signal SCb and to the cache 2 as control signal CSCb.
Control signal SCc from the system bus buffer 6 is inputted jointly to the CPU 1 and the cache 2, including a ready signal outputted from the memory system 3, as in the example of the cache system shown in FIG. 1. Signal SCd is a reread request signal outputted from the cache 2 to the CPU 1, and signal SCe is an operation enabling signal outputted from the cache 2 to the memory system 3.
An address signal AD1 is transmitted from the CPU 1 to both the cache 2 and the system bus buffer 6. An address signal AD2, which is used only where the CPU 1 is the bus master, is transmitted from the CPU 1 to both the cache 2 and a multiplexer 8. An address signal CAD2 which is used only where the cache 2 is the bus master is transmitted from the cache 2 to the multiplexer 8.
In response to a multiplexer control signal SC2 outputted from the cache 2, the multiplexer 8 selects either the address signal AD2 or CAD2 to output as an address signal AD3 to the system bus buffer 6.
A data signal SD is used as a duplex common signal between the CPU 1, cache 2, and system buffer 6. And .phi. designates a clock given to both the CPU 1 and the cache 2.
Next is a description of cases where the cache 2 hits and misses when the cache 2 is used by the CPU 1 in the data processor with a cache system of the prior art design described above. Assuming that the CPU 1 accesses to read a single data from the cache 2, the control signal SCa is then assumed to activate the cache 2.
In the CPU 1, one bus cycle consists of four timings T1 through T4 of the clock .phi. as shown in FIG. 2 (designated by T1234 in FIG. 2), and when the CPU 1 accesses to read the single data, this operation is completed in two bus cycles with no wait.
FIG. 2 is a timing chart illustrating the execution of a no wait operation when the cache 2 hits when the CPU 1 accesses to read the single data from the cache 2.
In FIG. 2, "CPU 1.fwdarw." designates signals outputted from the CPU 1, address signal AD1 (address value "m") designates the high order 28 bits of address, and address signal AD2 (address value "n") designates the low order 2 bits of address.
Control signals SCb10 and SCb11 are both included in control signal SCb. Signal SCb10 is asserted over one bus cycle in order to inform that the CPU 1 is starting a bus access for the external device. Signal SCb11 expects defined data and starts to be asserted from a rise of the timing T4 (hereinafter referred to as T4.uparw.) at which the control signal SCb10 is triggered.
"Cache 2.fwdarw." designates signals outputted from the cache 2. When the cache 2 hits, a ready signal SCb12, being included in control signal SCb and indicating a cache hit, is asserted and the data signal SD is outputted. At that time, the cache 2 is not the bus master, and signal SC1, which controls multiplexer 7, signal SC2, which controls multiplexer 8, and control signal SCe, which requires allowance of operation for the memory system 3, are all negated.
The operation where the cache 2 hits when the CPU1 accesses to read data is described next.
The bus cycle in which signal SCb10 is asserted by the CPU 1 and outputs of the next address signals AD1 and AD2 are initiated is called state SR1 of cache 2. During state SR1 of cache 2, the cache 2 decides whether to hit. As a result of this decision, when the cache 2 hits, during the next bus cycle, called state SR2H, both the ready signal SCb12 indicating that cache 2 hits and the data signal SD are asserted and data is transferred to the CPU 1.
Described next are procedures for reading data of 4 words including a single data which is requested for read-access by the CPU 1 when the cache 2 misses.
When the cache 2 decides to miss, the 4-word data including the single data which was accessed to be read by the CPU 1 are read from the memory system 3 connected to the system bus SB by a round robin method.
FIG. 3 is a timing chart illustrating the above state. Each of the control signals in FIG. 3 is low-active.
First, in state SR1, in which a read-access is requested by the CPU 1, when the cache 2 decides to miss, the ready signal SCb12, which is the cache hit signal, is not asserted during the next bus cycle, called state SR2M, but the control signal SCe for the system bus buffer 6 is asserted and reading operation is activated for the memory system 3.
The cache 2 asserts the multiplexer control signal SC2 for the multiplexer 8, and outputs the address signal CAD2 (value "n+1" obtained by an increment of "+1" to the address value "n" which is accessed by CPU 1) which is outputted from the multiplexer 8 as the address signal AD3 to the system bus buffer 6. For the address "n+1" a ready signal SCc12, which was transferred from the memory system 3 and which is included in the control signal SCc being outputted from the system bus buffer 6, is outputted both as the control signal SCb to the CPU 1 and as the signal CSCb12 included in the control signal CSCb to the cache 2, respectively, because the signal SC1, the control signal for the multiplexer 7, is being asserted.
At that time, the cache 2 requests to reread data for the CPU 1 by asserting the reread request signal SCd. For the address signal AD1 (address value "m") and address signal AD3 (address value "n+1"), the cache 2 inputs the data signal SD transferred from the memory system 3 as data of the first word, as well as the ready signal CSCb12, and the operation to read-access the data by the CPU 1 is completed.
Then, having received the request to reread, the CPU 1 outputs the same address values ("m", "n") as the previous cycle, activating a bus cycle. After that, in the same manner as in the case where the cache 2 reads the data of the first word, the CPU 1 sequentially provides increments of "n+2", "n+3" to the address signal CAD2 by the round robin method, reading data of the second word and third word. When reading data of the fourth word, the cache 2 does not assert the reread request signal SCd and reads both the ready signal SCc12 outputted from the system bus buffer 6 and the data of the fourth word into the CPU 1 and the cache 2 at the same time.
As described above, the CPU 1 reads the single data of the address values ("m", "n"), and the cache 2 reads the data of 4 words including the data which was accessed to be read by the CPU 1.
In a data processor with a conventional cache system art, such as the system described above, where the cache 2 misses when the CPU 1 accesses to read the single data for the cache 2, the CPU 1 can read the data which was accessed to be read only after it carries out the reread operation three times.
In other words, in order to read the required data, the CPU 1 required 12 bus cycles in the example shown in FIG. 3. Moreover, during the reread operation requested by cache 2, execution of the internal processing of the CPU 1, such as pipeline processing, can not be continued, which reduces the processing capability of the CPU 1. Consequently, more time is required for internal processing by the CPU 1 because the reread request is facilitated by CPU 1, which can necessitate many more bus cycles.
In order to avoid such inconveniences, it is necessary to try to reduce the number of bus cycles by additionally providing in the CPU 1 a circuit capable of being accessed to read data during any given cycle irrespective of a reread request.